The Cost Of Lithography For Chip Fabrication

The Cost Of Lithography For Chip Fabrication – Semiconductor Coating -Cheersonic

Start at 28nm, then progress from the first-generation FinFET node to the first EUV node to the first Gate All Around Nanosheet node (3nm and 2nm). Depending on the node examined, the percentage spent on lithography varies widely.

The evolution of lithography spending and deposition and etching has a large impact on the relative performance of major companies. As we tackle this, one of the most important aspects is the unit cost of exposure per DUV or EUV layer, and how many of them.

By using chiplets and MCMs, the number of products per wafer has increased by about 30%. If you assume a cost of $17,000 per wafer, then a single defect-free wafer costs $567, while a chiplet MCM costs $215 per defect-free wafer and $430 for two. Obviously if our design team should choose the chiplet MCM option ignoring any power consumption, die harvesting and packaging cost differences as they can save $136 per product!

What if we told you this chiplet MCM design is more expensive?

You probably won’t believe us, but let’s see how. In this hypothetical scenario, it is assumed that the product uses a foundry 5nm class node. Assuming the foundry sells these wafers for about $17,000, the gross margin is about 50%. Below is a breakdown of costs by consumables or process steps, including tool depreciation, maintenance costs, power usage, staff cost allocation, and more.

These numbers are far from our actual estimates, but what is consistent is that the largest cost center is lithography—nearly 1/3 of the cost of processing wafers. Lithography costs are just an average assumption. It can vary greatly depending on the die size you choose.

Photolithography tools indiscriminately expose silicon wafers. It needs to know where to expose with lithography and where not to. A photomask is something that contains the chip design and blocks light or allows light to pass through to expose the silicon. Leading 5nm foundry designs will have a dozen EUV photomasks and another dozens of DUV photomasks. Each of these photomasks corresponds to a feature or portion of a feature on the wafer and is unique to each chip design. Through a cycle of lithography and all other process steps, the foundry can make a specific 5nm chip on a wafer in about 10 weeks.

Typically, chip designs are smaller, so the photomask can contain multiple of the same designs as pictured above. Even then, most designs don’t fit perfectly into a 26mm x 33m field, so often part of this photomask is not exposed.

If a die is 12mm x 16mm, we can fit 4 dies on each reticle. The reticle utilization is very high here because only a small portion of the reticle is not exposed. For a 25mm x 32mm monolithic chip, we do not use 1mm in the slit and scan direction. The utilization rate of that marking line is also very high. For our chiplet, it’s 13.5mm x 32mm. The die is too large to fit 2 dies side by side on the reticle, so only 1 die per reticle.

What’s wrong with low reticle utilization, you might ask?

This becomes a huge cost issue because of what happens when we scale down to wafer-level processing. The silicon wafer placed in the lithography tool and the tool exposes a portion of the reticle area of ​​the silicon wafer at a time. If a full 26mm x 33mm reticle is used, the lithography tool traverses a 300mm silicon wafer with a minimum number of steps, 12 reticle areas wide and 10 reticle areas high. If the reticle utilization is low, the tool must pass over and over the wafer more times in each direction.

When comparing a 25mm x 32mm monolithic die on each wafer to a 13.5mm x 32mm chiplet MCM design, we need to span the wafer by a factor of 1.875!

Modern DUV and EUV tools have slit and scan capabilities. The slit (26mm) is exposed and it scans (33mm) across the reticle area.

Imagine if it were the other way around and the slits were halved. The throughput impact will be much larger.

When comparing our monolithic design to the chiplet MCM design, our lithography tool time increases significantly because the wafer has to be scanned 1.875 times. This is because a large part of the slit is not fully utilized. While there is still some efficiency in wafer loading time, most of the cost of a lithography tool is scan time. As a result, the internal cost per wafer has risen significantly.

In this hypothetical scenario, foundries now cost $2,174 more per wafer for lithography. That’s a huge cost increase that foundries won’t put up for high-volume customers who already have very tight margin deals. Assume that the foundry is priced by profit margin, so regardless of design, it can maintain a 50% gross margin.

The increased cost of underutilizing the slits in the reticle means that the foundry won’t sell these wafers for $17,000 to maintain a 50.2% gross margin. Instead, they will sell the wafers for $21,364. The cost of defect-free silicon for a monolithic product remains at $567. Instead of $215 per die, defect-free silicon costs $270. Instead of $430 per product, it’s $541.

The chiplet vs monolithic decision is now more difficult. Monolithic chips are likely to be cheaper to manufacture once packaging costs are factored in. Additionally, there are some power costs associated with the chiplet design. In this case, building a large monolithic chip is definitely better than using a chiplet/MCM.

This example is a worst-case scenario chosen to demonstrate reticle utilization points. There are many caveats to this simplistic and hypothetical analysis. Also, most of the other process nodes before 5nm and after we get into the gate have lower lithography costs compared to other process steps. Most chiplet architectures may increase rather than decrease reticle utilization.
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