2D Semiconductor Prospects Are Mixed

Researchers are working on a variety of new materials for future process nodes, but progress remains slow.

In recent years, two-dimensional semiconductors have emerged as a major potential solution to the problem of channel control in high-dimensional transistors. As the device shrinks, the channel thickness should scale down. Otherwise, the gate capacitance will not be sufficient to control the flow of current. Unfortunately, traps and other interfacial defects reduce carrier mobility and are more important in thin channels. The practical limit for silicon channel thickness appears to be around 3nm.

Two-dimensional transition metal dichalcogenides (TMDs), such as MoS and WSe, are interesting because they do not have out-of-plane dangling bonds, Stanford researcher Aravindh Kumar explained in an interview. The interaction of the top and bottom surfaces is limited and has little effect on the carrier behavior. MoS, in particular, is easy to synthesize and very stable.

Nonetheless, TMD deposition typically requires very high temperatures, well above the tolerances of commonly used bottom gate structures. For example, at imec, researcher Yuanyuan Shi and colleagues used a 1,000°C MOCVD process for MoS deposition. For this reason, most research on TMD devices has either used flakes exfoliated from bulk materials or free-standing layers grown on sapphire or silicon dioxide and then transferred.

While the layer transfer approach allows device research to proceed in parallel with process development, low temperature silicon compatible deposition processes are critical for the commercialization of TMD devices. In work reported at the IEEE Electron Devices Conference in December, Intel senior research engineer Kevin O’Brien and colleagues used pre-patterned metal oxide seeds to create nucleation sites for WS2 growth. Placing the metal source directly on the wafer avoids the use of solid metal oxide CVD sources. Controlled nucleation constrains the location of TMD crystals and therefore the grain boundaries associated with them.

The quality of free-standing MoS2 sheets depends on the deposition process and the original substrate. For example, in ACS Nano, University of Sussex researcher Manoj Tripathi and colleagues report that MoS grown by CVD on a silica substrate is in tension because it shrinks more than silica during cooling. More. The stored tension prevented the formation of wrinkles, a common problem in exfoliated MoS2.

Optimized Device Structure

As the film grows, the incoming molecules naturally assume the most favorable structure. In MoS2, direct deposition on sapphire is only more favorable than deposition on pre-existing MoS2 surface. As a result, islands with multiple MoS2 layers can be formed before the layers in contact with the substrate are completed. The edges of the islands do have dangling bonds, although making them more reactive. Shi’s imec group exploited edge reactivity by using post-deposition Cl etch to preferentially remove growth islands. The removal of islands improves the surface roughness and thickness uniformity of MOCVD films grown on sapphire.

Just as the future of silicon devices may depend on stacked nanosheets, TMD transistors may require multiple stacked channels to carry enough current. Peking University professor Xiong Xiong and colleagues fabricated stacked MoS2 channels in a single stack by transferring two large freestanding monolayers and then etching the material to the desired device dimensions. The same process can also be used to fabricate stacked complementary FETs, such as 2 for NMOS and WSe2 for PMOS.

As mentioned above, the best MoS2 devices at present depend on the back-gate design, in which the gate metal and gate oxide are deposited on a silicon substrate, and then a MoS2 layer is placed on top. This approach provides better device performance, but ultimately top-gate devices are more scalable. As with gate-all-around silicon transistors, dual gates with matched top and bottom capacitances will provide better channel control than single gates. Imec device integration engineer Xiangyu Wu and colleagues used a GdAlOx interlayer to improve capacitance matching in dual-gate MoS2 devices. Intermediate layers appear to reduce short-channel effects and improve threshold voltage control.

The process for fabricating free-standing MoS2 films is now mature enough to produce a statistically useful number of devices. Researchers are now reporting statistics on thousands of devices, a prerequisite for a scalable process. Unfortunately, these thousands of devices still lag behind silicon’s performance benchmarks. The connection to TMD was especially challenging.

Make Contact

There seem to be two sources of contact resistance. The defect-induced interstitial states arise from surface defects created during MoS deposition or during metal contact formation. The TSMC work used oxygen during deposition to passivate sulfur vacancies, a source of defects. Physical bombardment from thermally excited contact metals also contributes to increased contact resistance, Kumar proposed. The Stanford work used tin and indium, which are low-melting materials that can be deposited with minimal damage. When covered with gold, these metals form alloys that are stable above 450°C, making them compatible with existing BEOL processes.

Metal-induced gap states are another contributor to contact resistance, leading to Fermi level pinning. When the Fermi level is pinned, the energy barrier height at the interface is independent of the work function of the contacting metal and cannot be used to tune the threshold voltage. Semimetals are interesting as potential contacts because of their absence of band gaps and low density of states at the Fermi level. Therefore, they tend not to produce MIGS. Among semimetals, bismuth and tin have lower melting points, 271.5°C and 231.9°C, respectively. Antimony has a melting point of 630.6°C and is more suitable for processing. In the work presented by TSMC, Ang-Sheng Chou suggested that alloying 40% or more of antimony with bismuth could achieve co-optimization of contact barrier height, alloy conductivity, and melting point.

While Intel Group’s best contacts also use antimony, they caution that MoS 2 NMOS devices lag far behind silicon benchmarks, delivering 3X lower current than silicon at target subthreshold swing values. The situation is even worse for WSe2 PMOS devices. Their best device uses ruthenium contacts and achieves a current of 50 μA/μm at a subthreshold swing of 141 mV/decade.

Most 2D semiconductor FET demonstrations use top contacts because they are easier to manufacture. However, the edge contacts are smaller, which reduces the overall device footprint and also reduces aggressive scaling of channel lengths. Also, as mentioned above, the edges of 2D materials do have dangling bonds. The edge contacts may form covalent bonds compared to the weak van der Waals bonds present in the top contacts. TSMC’s Terry Hung’s work presented at IEDM 2020 shows that edge contacts eliminate Fermi-level pinning. [8] The interfacial surface (the “middle line” at the edge of the 2D material) forms a dipole whose effect decays rapidly with distance.

In Conclusion

Overall, the outlook for 2D semiconductor devices is mixed at best. While recent research has shown significant progress in material growth and contact fabrication, devices that can compete with cutting-edge silicon have yet to be demonstrated. When they do appear, they will likely involve different materials and processes than current fabs.

Source: semiengineering

Cheersonic is the leading developer and manufacturer of ultrasonic coating systems for applying precise, thin film coatings to protect, strengthen or smooth surfaces on parts and components for the microelectronics/electronics, alternative energy, medical and industrial markets, including specialized glass applications in construction and automotive.